Combined transistor sizing with buffer insertion for timing optimization

Yanbin Jiang; Sachin S. Sapatnekar; Cyrus Bamji; Juho Kim

Combined transistor sizing with buffer insertion for timing optimization

Yanbin Jiang
, Sachin S. Sapatnekar
, Cyrus Bamji
, Juho Kim

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.

Original language	English (US)
Pages (from-to)	605-608
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
State	Published - Jan 1 1998
Event	Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: May 11 1998 → May 14 1998

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@article{4681fe1e6cc3478aa6223cf46e093687,

title = "Combined transistor sizing with buffer insertion for timing optimization",

abstract = "This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.",

author = "Yanbin Jiang and Sapatnekar, \{Sachin S.\} and Cyrus Bamji and Juho Kim",

year = "1998",

month = jan,

day = "1",

language = "English (US)",

pages = "605--608",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1998 IEEE Custom Integrated Circuits Conference ; Conference date: 11-05-1998 Through 14-05-1998",

}

TY - JOUR

T1 - Combined transistor sizing with buffer insertion for timing optimization

AU - Jiang, Yanbin

AU - Sapatnekar, Sachin S.

AU - Bamji, Cyrus

AU - Kim, Juho

PY - 1998/1/1

Y1 - 1998/1/1

N2 - This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.

AB - This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.

UR - https://www.scopus.com/pages/publications/0031620164

UR - https://www.scopus.com/pages/publications/0031620164#tab=citedBy

M3 - Conference article

AN - SCOPUS:0031620164

SN - 0886-5930

SP - 605

EP - 608

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the 1998 IEEE Custom Integrated Circuits Conference

Y2 - 11 May 1998 through 14 May 1998

ER -

Combined transistor sizing with buffer insertion for timing optimization

Abstract

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