TY - JOUR
T1 - Combined transistor sizing with buffer insertion for timing optimization
AU - Jiang, Yanbin
AU - Sapatnekar, Sachin S.
AU - Bamji, Cyrus
AU - Kim, Juho
PY - 1998/1/1
Y1 - 1998/1/1
N2 - This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.
AB - This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.
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M3 - Conference article
AN - SCOPUS:0031620164
SN - 0886-5930
SP - 605
EP - 608
JO - Proceedings of the Custom Integrated Circuits Conference
JF - Proceedings of the Custom Integrated Circuits Conference
T2 - Proceedings of the 1998 IEEE Custom Integrated Circuits Conference
Y2 - 11 May 1998 through 14 May 1998
ER -