This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - Jan 1 1998|
|Event||Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA|
Duration: May 11 1998 → May 14 1998