Combined transistor sizing with buffer insertion for timing optimization

Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone.

Original languageEnglish (US)
Pages (from-to)605-608
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Jan 1 1998
EventProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: May 11 1998May 14 1998


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