Abstract
Graph convolutional networks (GCNs) have shown remarkable learning capabilities when processing graph-structured data found inherently in many application areas. GCNs distribute the outputs of neural networks embedded in each vertex over multiple iterations to take advantage of the relations captured by the underlying graphs. Consequently, they incur a significant amount of computation and irregular communication overheads, which call for GCN-specific hardware accelerators. To this end, this paper presents a communication-aware in-memory computing architecture (COIN) for GCN hardware acceleration. Besides accelerating the computation using custom compute elements (CE) and in-memory computing, COIN aims at minimizing the intra- and inter-CE communication in GCN operations to optimize the performance and energy efficiency. Experimental evaluations with widely used datasets show up to 105times improvement in energy consumption compared to state-of-the-art GCN accelerator.
Original language | English (US) |
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Pages (from-to) | 472-485 |
Number of pages | 14 |
Journal | IEEE Journal on Emerging and Selected Topics in Circuits and Systems |
Volume | 12 |
Issue number | 2 |
DOIs | |
State | Published - Jun 1 2022 |
Externally published | Yes |
Bibliographical note
Publisher Copyright:© 2011 IEEE.
Keywords
- Machine learning
- graph neural networks
- processing-in-memory
- resistive RAM