CODING SCHEME FOR CONCURRENT ERROR DETECTION/CORRECTION IN MULTISTAGE INTERCONNECTION NETWORKS.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A class of block codes is proposed for concurrent error detection and correction in packet-switching multistage interconnection networks (MINs). These codes represent a combination of interlaced parity checksum for the rows and a special modification of the Berger checksum for the columns. The codes are appropriate for line-limited permanent faults and area-limited transient faults predominant in VLSI and wafer-scale integration. The implementation of codes is simple and requires a minimal amount of network redundancy. The methods compare favorably with other coding techniques and can be used in fault-tolerant networks that need to tolerate transient as well as permanent faults in real time.

Original languageEnglish (US)
Title of host publicationProceedings of the International Conference on Parallel Processing
EditorsSartaj K. Sahni
PublisherPennsylvania State Univ Press
Pages755-758
Number of pages4
ISBN (Print)0271006080
StatePublished - Dec 1 1987
EventProc Int Conf Parallel Process 1987 - Universal Park, PA, USA
Duration: Aug 17 1987Aug 21 1987

Publication series

NameProceedings of the International Conference on Parallel Processing
ISSN (Print)0190-3918

Other

OtherProc Int Conf Parallel Process 1987
CityUniversal Park, PA, USA
Period8/17/878/21/87

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  • Cite this

    Cherkassky, V. (1987). CODING SCHEME FOR CONCURRENT ERROR DETECTION/CORRECTION IN MULTISTAGE INTERCONNECTION NETWORKS. In S. K. Sahni (Ed.), Proceedings of the International Conference on Parallel Processing (pp. 755-758). (Proceedings of the International Conference on Parallel Processing). Pennsylvania State Univ Press.