A class of block codes is proposed for concurrent error detection and correction in packet-switching multistage interconnection networks (MINs). These codes represent a combination of interlaced parity checksum for the rows and a special modification of the Berger checksum for the columns. The codes are appropriate for line-limited permanent faults and area-limited transient faults predominant in VLSI and wafer-scale integration. The implementation of codes is simple and requires a minimal amount of network redundancy. The methods compare favorably with other coding techniques and can be used in fault-tolerant networks that need to tolerate transient as well as permanent faults in real time.