CMOS MOBILITY DEGRADATION COEFFICIENTS AT LOW TEMPERATURES.

Stephen A Campbell, P. Andersen

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

An AC measurement technique is applied to NMOS and PMOS devices fabricated using a 1. 25 mu m CMOS process. The parasitic resistance and mobility degradation coefficients have been extracted for temperatures between 25 K and 300 K. The NMOS parasitic resistance stays flat with temperature while the PMOS resistance rises sharply below 200 K, probably due to the light source/drain diffusion doping. The mobility reduction parameter theta , shows a clear 1/T behavior between 100 K and room temperature, with theta approaching unity for the PMOS devices. This may have serious implications for the performance of highly scaled devices which operate at high transverse electrical fields.

Original languageEnglish (US)
Pages (from-to)17-19
Number of pages3
JournalIEE Proceedings I: Solid State and Electron Devices
Volume135
Issue number1
DOIs
StatePublished - Jan 1 1988

Fingerprint Dive into the research topics of 'CMOS MOBILITY DEGRADATION COEFFICIENTS AT LOW TEMPERATURES.'. Together they form a unique fingerprint.

Cite this