CMOS circuit design of threshold gates with hysteresis

Research output: Contribution to journalConference article

92 Scopus citations

Abstract

M-of-N threshold gates with hysteresis form a class of circuit elements that have important application in NULL Convention LogicTM, a novel asynchronous logic design methodology. General design guidelines for these M-of-N gates are presented using CMOS technology. Three types of circuit implementations are discussed: static, semi-static and dynamic. In addition, initialization techniques are presented for use in establishing a known initial state.

Original languageEnglish (US)
Pages (from-to)61-64
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
StatePublished - Jan 1 1998
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: May 31 1998Jun 3 1998

Fingerprint Dive into the research topics of 'CMOS circuit design of threshold gates with hysteresis'. Together they form a unique fingerprint.

  • Cite this