Clock tree synthesis for multi-chip modules

Keyphrases

• Clock Tree 100%
• Clock Tree Synthesis 100%
• Multichip Modules 100%
• Near-zero 50%
• Clock Signal 50%
• Buffer Insertion 50%
• Non-monotonic Behavior 50%
• Fully Distributed 50%
• SPICE Simulation 50%
• RLC Model 50%
• Slew Rate 50%

Computer Science

• Buffer Insertion 100%
• Experimental Result 100%