Clock tree synthesis for multi-chip modules

Daksh Lehther, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


While designing interconnect for MCM's, one must take into consideration the distributed RLC effects, due to which signals may display nonmonotonic behavior and substantial ringing. This paper considers the problem of designing clock trees for MCM's. A fully distributed RLC model is utilized for AWE-based analysis and synthesis, and appropriate measures are taken to ensure adequate signal damping and for buffer insertion to satisfy constraints on the clock signal slew rate. Experimental results, verified by SPICE simulations, show that this method can be used to build clock trees with near-zero skews.

Original languageEnglish (US)
Pages (from-to)50-53
Number of pages4
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
StatePublished - Dec 1 1996


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