Clock distribution using multiple voltages

Jatuchai Pangjun, Sachin S. Sapatnekar

Research output: Contribution to conferencePaper

12 Scopus citations

Abstract

Clock networks account for a significant fraction of the power dissipation of a chip and are critical to the performance. This paper presents theory and algorithms for building a low power clock tree. Two low power schemes are used: a reduced swing scheme and one using multiple supply voltages. We analyze the issue of tree construction and present conclusions relevant to various technology generations according to the National Technology Roadmap of Semiconductors (NTRS). Our experimental results show that the power could be saved an average of 45% for a 0.25 μm technology using multiple supply voltages, and 31% using reduced swing buffers.

Original languageEnglish (US)
Pages145-150
Number of pages6
DOIs
StatePublished - 1999
EventProceedings of the 1999 International Conference on Low Power Electronics and Design (ISLPED) - San Diego, CA, USA
Duration: Aug 16 1999Aug 17 1999

Conference

ConferenceProceedings of the 1999 International Conference on Low Power Electronics and Design (ISLPED)
CitySan Diego, CA, USA
Period8/16/998/17/99

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    Pangjun, J., & Sapatnekar, S. S. (1999). Clock distribution using multiple voltages. 145-150. Paper presented at Proceedings of the 1999 International Conference on Low Power Electronics and Design (ISLPED), San Diego, CA, USA, . https://doi.org/10.1145/313817.313902