Circuit techniques for enhancing the clock data compensation effect under resonant supply noise

Dong Jiao, Jie Gu, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Recent publications have shown that clock jitter can improve timing margin through the compensation effect between the clock cycle and the datapath delay under the influence of resonant supply noise. In this paper, novel phase-shifted clock buffer designs are proposed to enhance this "beneficial jitter effect". Compared with existing designs, our design saves 85% of the clock buffer area while achieving a similar 10% increase in the maximum operating frequency for typical pipeline circuits. Measurement results are presented from a test chip implemented in a 1.2V, 65nm process.

Original languageEnglish (US)
Title of host publication2009 IEEE Custom Integrated Circuits Conference, CICC '09
Pages29-32
Number of pages4
DOIs
StatePublished - Dec 1 2009
Event2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
Duration: Sep 13 2009Sep 16 2009

Other

Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
CountryUnited States
CitySan Jose, CA
Period9/13/099/16/09

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    Jiao, D., Gu, J., & Kim, C. H. (2009). Circuit techniques for enhancing the clock data compensation effect under resonant supply noise. In 2009 IEEE Custom Integrated Circuits Conference, CICC '09 (pp. 29-32). [5280918] https://doi.org/10.1109/CICC.2009.5280918