Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs

Sravan K. Marella, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents an approach for analyzing stress in 2-D and 3-D integrated circuits (ICs) due to postmanufacturing thermal mismatch. For both 2D-ICs and 3D-ICs, shallow trench isolation (STI) induces thermal residual stress in active silicon. For 3D-ICs, through-silicon vias (TSVs) act as an additional source of stress. Together, the sources of stress cause changes in the delay and power of the circuit. We develop an analytical model based on inclusion theory in micromechanics to accurately estimate the stresses and strains induced in the active region by surrounding STI in a layout. The TSV-induced stress depends on the location of the transistor with respect to the TSVs. Therefore, these stresses result in placement-dependent variations in the transistor mobilities and threshold voltages of the active devices, and we propagate these effects to circuit-level performance. At the transistor level, the stress state is translated into mobility and threshold voltage variations using piezoresistivity and band deformation potential models, respectively. At the gate level, the computed changes in transistor electrical parameters are used to predict gate-level delay and leakage power changes for single-fingered and multifingered layout styles, which are subsequently used to predict circuit-level delay and leakage power for a given placement.

Original languageEnglish (US)
Article number8463602
Pages (from-to)2907-2920
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume26
Issue number12
DOIs
StatePublished - Dec 2018

Bibliographical note

Funding Information:
Manuscript received March 8, 2018; revised June 25, 2018; accepted July 31, 2018. Date of publication September 13, 2018; date of current version November 30, 2018. This work was supported by the NSF under Award CCF-1421606. (Corresponding author: Sravan K. Marella.) S. K. Marella was with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. He is now with Logic Technology Development, Intel Corporation, Santa Clara, CA 95054 USA (e-mail: sravan@umn.edu).

Keywords

  • 3-D-integrated circuits (IC)
  • finite-element method (FEM)
  • shallow trench isolation (STI)
  • static timing analysis

Fingerprint Dive into the research topics of 'Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs'. Together they form a unique fingerprint.

Cite this