Circuit-level delay modeling considering both TDDB and NBTI

Hong Luo; Xiaoming Chen; Jyothi Velamala; Yu Wang; Yu Cao; Vikas Chandra; Yuchun Ma; Huazhong Yang

doi:10.1109/ISQED.2011.5770697

Circuit-level delay modeling considering both TDDB and NBTI

Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

With aggressive scaling down of the technology node, the time-dependent dielectric breakdown (TDDB) and negative biased temperature instability (NBTI) are becoming key challenges for circuit designers. Both TDDB and NBTI significantly degrade the electrical characteristic of the CMOS devices. A delay model considering TDDB and NBTI is proposed in this paper. The output degradation of the breakdown gate is considered in circuit-level delay analysis. Traditionally, it is considered the TDDB degradation always degrades the circuit delay. However, this paper shows the TDDB effect may boost up the circuit speed. The spatial correlation of TDDB effect is also demonstrated in this paper and shows the difference of 40% in circuit delay depending on the location of the breakdown gate in the signal path.

Original language	English (US)
Title of host publication	Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages	14-21
Number of pages	8
DOIs	https://doi.org/10.1109/ISQED.2011.5770697
State	Published - 2011
Externally published	Yes
Event	12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA, United States Duration: Mar 14 2011 → Mar 16 2011

Publication series

Name	Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Conference

Conference	12th International Symposium on Quality Electronic Design, ISQED 2011
Country/Territory	United States
City	Santa Clara, CA
Period	3/14/11 → 3/16/11

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10.1109/ISQED.2011.5770697

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Luo, H., Chen, X., Velamala, J., Wang, Y., Cao, Y., Chandra, V., Ma, Y., & Yang, H. (2011). Circuit-level delay modeling considering both TDDB and NBTI. In Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011 (pp. 14-21). Article 5770697 (Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011). https://doi.org/10.1109/ISQED.2011.5770697

Circuit-level delay modeling considering both TDDB and NBTI. / Luo, Hong; Chen, Xiaoming; Velamala, Jyothi et al.
Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011. 2011. p. 14-21 5770697 (Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Luo, H, Chen, X, Velamala, J, Wang, Y, Cao, Y, Chandra, V, Ma, Y & Yang, H 2011, Circuit-level delay modeling considering both TDDB and NBTI. in Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011., 5770697, Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, pp. 14-21, 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, CA, United States, 3/14/11. https://doi.org/10.1109/ISQED.2011.5770697

@inproceedings{6acbd23e737e441abaaab25dfe804cc3,

title = "Circuit-level delay modeling considering both TDDB and NBTI",

abstract = "With aggressive scaling down of the technology node, the time-dependent dielectric breakdown (TDDB) and negative biased temperature instability (NBTI) are becoming key challenges for circuit designers. Both TDDB and NBTI significantly degrade the electrical characteristic of the CMOS devices. A delay model considering TDDB and NBTI is proposed in this paper. The output degradation of the breakdown gate is considered in circuit-level delay analysis. Traditionally, it is considered the TDDB degradation always degrades the circuit delay. However, this paper shows the TDDB effect may boost up the circuit speed. The spatial correlation of TDDB effect is also demonstrated in this paper and shows the difference of 40% in circuit delay depending on the location of the breakdown gate in the signal path.",

author = "Hong Luo and Xiaoming Chen and Jyothi Velamala and Yu Wang and Yu Cao and Vikas Chandra and Yuchun Ma and Huazhong Yang",

year = "2011",

doi = "10.1109/ISQED.2011.5770697",

language = "English (US)",

isbn = "9781612849140",

series = "Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011",

pages = "14--21",

booktitle = "Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011",

note = "12th International Symposium on Quality Electronic Design, ISQED 2011 ; Conference date: 14-03-2011 Through 16-03-2011",

}

TY - GEN

T1 - Circuit-level delay modeling considering both TDDB and NBTI

AU - Luo, Hong

AU - Chen, Xiaoming

AU - Velamala, Jyothi

AU - Wang, Yu

AU - Cao, Yu

AU - Chandra, Vikas

AU - Ma, Yuchun

AU - Yang, Huazhong

PY - 2011

Y1 - 2011

N2 - With aggressive scaling down of the technology node, the time-dependent dielectric breakdown (TDDB) and negative biased temperature instability (NBTI) are becoming key challenges for circuit designers. Both TDDB and NBTI significantly degrade the electrical characteristic of the CMOS devices. A delay model considering TDDB and NBTI is proposed in this paper. The output degradation of the breakdown gate is considered in circuit-level delay analysis. Traditionally, it is considered the TDDB degradation always degrades the circuit delay. However, this paper shows the TDDB effect may boost up the circuit speed. The spatial correlation of TDDB effect is also demonstrated in this paper and shows the difference of 40% in circuit delay depending on the location of the breakdown gate in the signal path.

AB - With aggressive scaling down of the technology node, the time-dependent dielectric breakdown (TDDB) and negative biased temperature instability (NBTI) are becoming key challenges for circuit designers. Both TDDB and NBTI significantly degrade the electrical characteristic of the CMOS devices. A delay model considering TDDB and NBTI is proposed in this paper. The output degradation of the breakdown gate is considered in circuit-level delay analysis. Traditionally, it is considered the TDDB degradation always degrades the circuit delay. However, this paper shows the TDDB effect may boost up the circuit speed. The spatial correlation of TDDB effect is also demonstrated in this paper and shows the difference of 40% in circuit delay depending on the location of the breakdown gate in the signal path.

UR - http://www.scopus.com/inward/record.url?scp=79959232668&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79959232668&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2011.5770697

DO - 10.1109/ISQED.2011.5770697

M3 - Conference contribution

AN - SCOPUS:79959232668

SN - 9781612849140

T3 - Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

SP - 14

EP - 21

BT - Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

T2 - 12th International Symposium on Quality Electronic Design, ISQED 2011

Y2 - 14 March 2011 through 16 March 2011

ER -

Circuit-level delay modeling considering both TDDB and NBTI

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