Abstract
Electromigration (EM) in signal interconnects can induce voids, and the evolution of these voids may cause the wire resistance to increase with time. Previous approaches use the mean time to failure metric based either on a fixed resistance increase or open circuit failure criterion. This work shows that even noncatastrophic EM on critical paths may cause performance degradation, resulting in incorrect circuit operation. HSPICE-based Monte Carlo simulations on a set of on-chip structures are performed to quantify the impact of EM on circuit performance degradation.
Original language | English (US) |
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Title of host publication | 2015 IEEE International Reliability Physics Symposium, IRPS 2015 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 3D31-3D37 |
ISBN (Electronic) | 9781467373623 |
DOIs | |
State | Published - May 26 2015 |
Event | IEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States Duration: Apr 19 2015 → Apr 23 2015 |
Publication series
Name | IEEE International Reliability Physics Symposium Proceedings |
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Volume | 2015-May |
ISSN (Print) | 1541-7026 |
Other
Other | IEEE International Reliability Physics Symposium, IRPS 2015 |
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Country/Territory | United States |
City | Monterey |
Period | 4/19/15 → 4/23/15 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.
Keywords
- AC EM analysis
- clock skew
- delay
- technology scaling