Circuit delay variability due to wire resistance evolution under AC electromigration

Vivek Mishra, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Electromigration (EM) in signal interconnects can induce voids, and the evolution of these voids may cause the wire resistance to increase with time. Previous approaches use the mean time to failure metric based either on a fixed resistance increase or open circuit failure criterion. This work shows that even noncatastrophic EM on critical paths may cause performance degradation, resulting in incorrect circuit operation. HSPICE-based Monte Carlo simulations on a set of on-chip structures are performed to quantify the impact of EM on circuit performance degradation.

Original languageEnglish (US)
Title of host publication2015 IEEE International Reliability Physics Symposium, IRPS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages3D31-3D37
Volume2015-May
ISBN (Electronic)9781467373623
DOIs
StatePublished - Jan 1 2015
EventIEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States
Duration: Apr 19 2015Apr 23 2015

Other

OtherIEEE International Reliability Physics Symposium, IRPS 2015
Country/TerritoryUnited States
CityMonterey
Period4/19/154/23/15

Keywords

  • AC EM analysis
  • clock skew
  • delay
  • technology scaling

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