Circuit-aware on-chip inductance extraction

Research output: Contribution to journalConference article

2 Scopus citations

Abstract

In this paper we propose a practical approach for on-chip inductance extraction. This approach differs from previous methods in that it uses circuit characteristics to obtain a sparse, stable and symmetric inductance matrix, using the concept of resistance dominant and inductance dominant lines. Experimental results show that only the important inductance terms related to strong inductance couplings are included in the sparsified inductance matrix to ensure a specified predefined accuracy. For a good design, the sparsification can reach 95% by setting an acceptable delay error of 10% and oscillation magnitude error of 2%.

Original languageEnglish (US)
Pages (from-to)245-248
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - Jan 1 2001
EventIEEE 2001 Custom Integrated Circuits Conference - San Diego, CA, United States
Duration: May 6 2001May 9 2001

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