Chopper stabilized sub 1V reference voltage in 65nm CMOS

Rakesh Kumar Palani, Aravindhan Rangarajan, Ramesh Harjani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A sub 1V reference circuit is proposed, that exploits the CTAT and PTAT voltages in the beta multiplier circuit to attain a stable voltage with temperature and power supply. A one-time calibration is integrated in the architecture to get a good performance over process. Further, chopper stabilization is proposed in the circuit itself rather than in the OTA to acheive a 4.8x reduction in integrated flicker noise voltage without increasing power dissipation. The prototype designed in TSMC's 65nm general purpose CMOS for 236mV nominal voltage, shows a temperature coefficient of 18 ppm/°C from -40 to 100°C with a power supply ranging from 0.8 to 2V while consuming 16μA current. Simulated variation in the reference voltage is 0.7mV with power supply at nominal temperature.

Original languageEnglish (US)
Title of host publicationIEEE 58th International Midwest Symposium on Circuits and Systems
Subtitle of host publicationClimbing to New Heights, MWSCAS 2015 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467365574
DOIs
StatePublished - Sep 28 2015
Event58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015 - Fort Collins, United States
Duration: Aug 2 2015Aug 5 2015

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2015-September
ISSN (Print)1548-3746

Other

Other58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015
CountryUnited States
CityFort Collins
Period8/2/158/5/15

Keywords

  • CMOS
  • subbandgap reference voltage circuit
  • temperature sensitivity

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