Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit

Qianying Tang, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

The impact of random telegraph noise (RTN) on circuit delay has been experimentally verified using a dual ring oscillator (ROSC) array test structure. The proposed on-chip monitor utilizes the tested-and-proven beat frequency detection technique to measure RTN-induced frequency shifts with high precision (>0.01%) and short sampling time (>1μs). The main idea is to pair an ROSC in the first array with an ROSC having a similar frequency from a second array, so that the frequency measurement resolution is not compromised at sub- 0.5-V supply voltages. RTN-induced frequency shifts at different supply voltages, temperatures, and stress conditions were measured from a 32-nm high-k metal-gate test chip. The impact of RTN on logic and SRAM performance was analyzed based on the measured RTN data. We also present the quantitative results of logic timing margin and SRAM noise margin, with and without RTN. According to this paper, RTN appears to have a modest 1% impact on circuit operating frequency in 32 nm, even under pessimistic conditions (i.e., Vdd = 0.6 V, multiple RTN traps in circuit path).

Original languageEnglish (US)
Article number7892967
Pages (from-to)1655-1663
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume52
Issue number6
DOIs
StatePublished - Jun 2017

Keywords

  • Logic timing margin
  • SRAM noise margin
  • random telegraph noise (RTN)
  • ring oscillator (ROSC)

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