The device design and characteristics of sub-100 nm strained Si N- and PMOSFETs were discussed. A enhancement of 110% was observed in the strained Si devices with 1.2% tensile strain, along with a 45% increase in the peak hole mobility. A comparison of current-voltage characteristics of 100 nm PFETs was done. The strained Si (SS) PFETs showed comparable subthreshold characteristics while showing higher current drive.
|Original language||English (US)|
|Number of pages||2|
|State||Published - Jan 1 2002|
|Event||2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States|
Duration: Jun 11 2002 → Jun 13 2002
|Other||2002 Symposium on VLSI Technology Digest of Technical Papers|
|Period||6/11/02 → 6/13/02|