Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

K. Rim, J. Chu, H. Chen, K. A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, H. S. Wong

Research output: Contribution to conferencePaper

176 Scopus citations

Abstract

The device design and characteristics of sub-100 nm strained Si N- and PMOSFETs were discussed. A enhancement of 110% was observed in the strained Si devices with 1.2% tensile strain, along with a 45% increase in the peak hole mobility. A comparison of current-voltage characteristics of 100 nm PFETs was done. The strained Si (SS) PFETs showed comparable subthreshold characteristics while showing higher current drive.

Original languageEnglish (US)
Pages98-99
Number of pages2
StatePublished - Jan 1 2002
Event2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States
Duration: Jun 11 2002Jun 13 2002

Other

Other2002 Symposium on VLSI Technology Digest of Technical Papers
CountryUnited States
CityHonolulu, HI
Period6/11/026/13/02

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