Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization

Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar

Research output: Contribution to journalArticle

8 Scopus citations

Abstract

Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mechanism in nanometer-scale technologies. This paper addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently considerably reducing the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved by about 2.5 × - 161 × by avoiding the EM-critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.

Original languageEnglish (US)
Article number7156109
Pages (from-to)220-231
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume35
Issue number2
DOIs
StatePublished - Feb 2016

Keywords

  • Cell-internal Signal Electromigration
  • Current Divergence
  • EDA
  • Electromigration
  • Joule Heating
  • Physical Design

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