CATALYST: Planning layer directives for effective design closure

Yaoguang Wei, Zhuo Li, Cliff Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

For the last several technology generations, VLSI designs in new technology nodes have had to confront the challenges associated with reduced scaling in wire delays. The solution from industrial back-end-of-line process has been to add more and more thick metal layers to the wiring stacks. However, existing physical synthesis tools are usually not effective in handling these new thick layers for design closure. To fully leverage these degrees of freedom, it is essential for the design flow to provide better communication among the timer, the router, and different optimization engines. This work proposes a new algorithm, CATALYST, to perform congestion- and timing-aware layer directive assignment. Our flow balances routing resources among metal stacks so that designs benefit from the availability of thick metal layers by achieving improved timing and buffer usage reduction while maintaining routability. Experiments demonstrate the effectiveness of the proposed algorithm.

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe, DATE 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1873-1878
Number of pages6
ISBN (Print)9783981537000
DOIs
StatePublished - Jan 1 2013
Event16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013 - Grenoble, France
Duration: Mar 18 2013Mar 22 2013

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other16th Design, Automation and Test in Europe Conference and Exhibition, DATE 2013
CountryFrance
CityGrenoble
Period3/18/133/22/13

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  • Cite this

    Wei, Y., Li, Z., Sze, C., Hu, S., Alpert, C. J., & Sapatnekar, S. S. (2013). CATALYST: Planning layer directives for effective design closure. In Proceedings - Design, Automation and Test in Europe, DATE 2013 (pp. 1873-1878). [6513819] (Proceedings -Design, Automation and Test in Europe, DATE). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.7873/date.2013.373