Carrier mobility enhancement in strained Si-On-Insulator fabricated by wafer bonding

L. J. Huang, J. O. Chu, S. Goma, C. P. D'Emic, S. J. Koester, D. F. Canaperi, P. M. Mooney, S. A. Cordes, J. L. Speidell, R. M. Anderson, H. S. Philip Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

37 Scopus citations

Abstract

N- and p-MOSFETs have been fabricated in strained Si on SiGe on insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-On-Insulator (SGOI) substrates. Mobility enhancement of 46% for electrons and 60-80% for holes (for 20%-25% Ge content, respectively) has been demonstrated in SSOI MOSFETs. This could lead to next generation device performance enhancement.

Original languageEnglish (US)
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages57-58
Number of pages2
EditionTECHNOLOGY SYMP.
StatePublished - Jan 1 2001
Event2001 VLSI Technology Symposium - Kyoto, Japan
Duration: Jun 12 2001Jun 14 2001

Other

Other2001 VLSI Technology Symposium
CountryJapan
CityKyoto
Period6/12/016/14/01

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