Capturing post-silicon variations using a representative critical path

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32 Scopus citations


In nanoscale technologies that experience large levels of process variation, post-silicon adaptation is an important step in circuit design. These adaptation techniques are often based on measurements of a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit after manufacturing. For realistic circuits, where the number of critical paths can be large, the notion of using a single critical path is too simplistic. This paper overcomes this problem by introducing the idea of synthesizing a representative critical path (RCP), which captures these complexities of the variations. We first prove that the requirement on the RCP is that it should be highly correlated with the circuit delay. Next, we present three novel algorithms to automatically build the RCP. Our experimental results demonstrate that over a number of samples of manufactured circuits, the delay of the RCP captures the worst case delay of the manufactured circuit. The average prediction error of all circuits is shown to be below 2.8% for all three approaches. For both our approach and the critical path replica method, it is essential to guard-band the prediction to ensure pessimism: on average our approach requires a guard band 31% smaller than for the critical path replica method.

Original languageEnglish (US)
Article number5395738
Pages (from-to)211-222
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number2
StatePublished - Feb 2010

Bibliographical note

Funding Information:
Manuscript received June 9, 2009; revised August 21, 2009. Current version published January 22, 2010. This work was supported in part by the National Science Foundation under Awards CCF-0205227 and CCF-0541367, and by the Semiconductor Research Corporation under Contract 2007-TJ-1572. This paper was recommended by Associate Editor P. Saxena.


  • Algorithms
  • Circuit analysis
  • Design automation
  • Timing


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