Calculation of minimum number of registers in 2-D discrete wavelet transforms using lapped block processing

Tracy C. Denk, Keshab K. Parhi

Research output: Contribution to journalConference article

20 Citations (Scopus)

Abstract

This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform.

Original languageEnglish (US)
Pages (from-to)77-80
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
StatePublished - Dec 1 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: May 30 1994Jun 2 1994

Fingerprint

Discrete wavelet transforms
FIR filters
Electric delay lines
Processing

Cite this

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abstract = "This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform.",
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AB - This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform.

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