### Abstract

This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform.

Original language | English (US) |
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Pages (from-to) | 77-80 |

Number of pages | 4 |

Journal | Proceedings - IEEE International Symposium on Circuits and Systems |

Volume | 3 |

State | Published - Dec 1 1994 |

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### Cite this

**Calculation of minimum number of registers in 2-D discrete wavelet transforms using lapped block processing.** / Denk, Tracy C.; Parhi, Keshab K.

Research output: Contribution to journal › Article

}

TY - JOUR

T1 - Calculation of minimum number of registers in 2-D discrete wavelet transforms using lapped block processing

AU - Denk, Tracy C.

AU - Parhi, Keshab K

PY - 1994/12/1

Y1 - 1994/12/1

N2 - This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform.

AB - This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform.

UR - http://www.scopus.com/inward/record.url?scp=0028582309&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028582309&partnerID=8YFLogxK

M3 - Article

VL - 3

SP - 77

EP - 80

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -