Abstract
This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 77-80 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 3 |
| State | Published - Dec 1 1994 |
| Event | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: May 30 1994 → Jun 2 1994 |