Cache Coherence in Large-Scale Shared-Memory Multiprocessors: Issues and Comparisons

Due to data spreading among processors and due to the cache coherence problem, private data caches have not been as effective in reducing the average memory delay in multiprocessors as in uniprocessors. A wide variety of mechanisms have been proposed for mamtammg cache coherence m large-scale shared-memory multiprocessors, makmg it difficult to compare them perform ante and implementation implications To help the computer architect understand some of the trade-offs involved, this paper surveys current cache coherence mechanisms and identifies several issues critical to thendeslgn These design issues include: (1) the cokerence detection strategy, through which possibly incoherent memory accesses are detected either statically at compile-time, or dynamically at run-time; (2) the coherence enforcement strategy, such as updating or mvalidatmg, used to ensure that stale cache entries are never referenced by a processor; (3) how the preczslon of block-sharzng znformatzon can be changed to trade-off the Implementation cost and performance of the coherence mechamsm; and (4) how the cache block szze affects the performance of the memory system. Trace-driven simulations are used to compare the performance and implementation impacts of these different issues, Additionally, hybrzd strategies are presented that can enhance tbe performance of the multiprocessor memory system by combining several different coherence mecb anisms into a single system.