TY - GEN
T1 - Buffering global interconnects in structured ASIC design
AU - Zhang, Tianpei
AU - Sapatnekar, Sachin S
PY - 2005/12/1
Y1 - 2005/12/1
N2 - Structured ASICs present an attractive alternative to reducing de-sign costs and turnaround times in nanometer designs. As with conven-tional ASICs, such designs require global wires to be buffered. However, via-programmable designs must prefabricate and preplace buffers in the layout. This oaper proposes a novel and accurate statistical estimation technique jo. distributing prefabricated buffers through a layout. It employs Rent's rule to estimate the buffer distribution required for the layout, so that an appropriate structured ASIC may be selected for the design. Experimental results show that the estimation for a uniform buffer distribution is accurate and economic.
AB - Structured ASICs present an attractive alternative to reducing de-sign costs and turnaround times in nanometer designs. As with conven-tional ASICs, such designs require global wires to be buffered. However, via-programmable designs must prefabricate and preplace buffers in the layout. This oaper proposes a novel and accurate statistical estimation technique jo. distributing prefabricated buffers through a layout. It employs Rent's rule to estimate the buffer distribution required for the layout, so that an appropriate structured ASIC may be selected for the design. Experimental results show that the estimation for a uniform buffer distribution is accurate and economic.
UR - http://www.scopus.com/inward/record.url?scp=84861426445&partnerID=8YFLogxK
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M3 - Conference contribution
AN - SCOPUS:84861426445
SN - 0780387368
SN - 9780780387362
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 23
EP - 26
BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
T2 - 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Y2 - 18 January 2005 through 21 January 2005
ER -