Buffering global interconnects in structured ASIC design

Tianpei Zhang, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

Structured ASICs present an attractive alternative to reducing de-sign costs and turnaround times in nanometer designs. As with conven-tional ASICs, such designs require global wires to be buffered. However, via-programmable designs must prefabricate and preplace buffers in the layout. This oaper proposes a novel and accurate statistical estimation technique jo. distributing prefabricated buffers through a layout. It employs Rent's rule to estimate the buffer distribution required for the layout, so that an appropriate structured ASIC may be selected for the design. Experimental results show that the estimation for a uniform buffer distribution is accurate and economic.

Original languageEnglish (US)
Title of host publicationProceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages23-26
Number of pages4
StatePublished - Dec 1 2005
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: Jan 18 2005Jan 21 2005

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume1

Other

Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CountryChina
CityShanghai
Period1/18/051/21/05

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