## Abstract

A description is given of a word-parallel bit-parallel architecture for implementation of very fast recursive filters based on block state descriptions. The throughput is maximized by parallel processing, and by pipelining all computations at the bit level. The throughput with block size one is limited by the speed of one-bit latched full adders. Unbounded sampling rates beyond this can be achieved by increasing the block size. The feedback in recursive filters limits the opportunity to pipeline all operations at the bit level. This difficulty is overcome by recasting the structure of the algorithm and using look-ahead computation to derive an equivalent recursive filter description which is pipelinable at the bit level. The complexity of this implementation in terms of one-bit latched full adders for this architecture is O(NLW**3 ) and the latency in terms of input sample periods is O(L**2 W**2 , where N is the filter order. W is the word length, and L is the block size.

Original language | English (US) |
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Title of host publication | Unknown Host Publication Title |

Publisher | IEEE |

Pages | 284-289 |

Number of pages | 6 |

ISBN (Print) | 0818607351 |

State | Published - Dec 1 1986 |