BDD decomposition for delay oriented pass transistor logic synthesis

Keyphrases

• Pass Transistor Logic 100%
• Binary Decision Diagram 100%
• Logic Synthesis 100%
• Static CMOS 50%
• Maximum Flow 25%
• Cost Function 25%
• Control Circuit 25%
• Arithmetic Logic Unit 25%
• CMOS Implementation 25%
• Delay Reduction 25%
• Bipartition 25%
• Logic Control 25%
• Flow Network Graph 25%

Computer Science

• Logic Synthesis 100%
• binary decision diagram 100%
• Arithmetic Logic Unit 25%
• Experimental Result 25%