Abstract
Recent advances in auto-generating analog and mixed-signal (AMS) circuits use standard digital tool flows to compose AMS circuits from a combination of digital standard cells and a set of auxiliary cells (auxcells). Until now, generating auxcell layouts for each new PDK was the last manual step in the flow for auto-generating AMS components, which limited the available auxcells and reduced the optimality of the auto-generated AMS designs. To solve this, we propose AuxcellGen, a framework to auto-generate auxcell layouts and performance models. Aux-cellGen generates a parasitic-aware auxcell performance model using a neural network (NN), auto-sizes and optimizes auxcell schematics for a given design target, and auto-generates auxcell layouts. The framework is demonstrated by auto-generating tristate buffer auxcells for PLLs and sense-amplifier auxcells for SRAM across a range of user specifications that are compatible with standard cell and memory bitcell pitch.
Original language | English (US) |
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Title of host publication | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9783981926378 |
DOIs | |
State | Published - 2023 |
Event | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Antwerp, Belgium Duration: Apr 17 2023 → Apr 19 2023 |
Publication series
Name | Proceedings -Design, Automation and Test in Europe, DATE |
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Volume | 2023-April |
ISSN (Print) | 1530-1591 |
Conference
Conference | 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 |
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Country/Territory | Belgium |
City | Antwerp |
Period | 4/17/23 → 4/19/23 |
Bibliographical note
Funding Information:VI. ACKNOWLEDGEMENT This work was funded in part by Defense Advanced Research Projects Agency (DARPA) under agreement no. FA8650-18-2-7844 and as part of the ALIGN project, under NIWC Contract N660011824048.
Publisher Copyright:
© 2023 EDAA.
Keywords
- cell-based layout automation
- circuit optimization
- memory layout generation
- surrogate modelling