Abstract
This work aims to investigate the automatic generation of Verilog code, representing digital circuits through Grammatical Evolution (GE). Preliminary tests using a simple full adder generation problem have been performed.
| Original language | English (US) |
|---|---|
| Title of host publication | GECCO 2005 - Genetic and Evolutionary Computation Conference |
| Publisher | Association for Computing Machinery |
| Pages | 394-397 |
| Number of pages | 4 |
| ISBN (Print) | 1595930108, 9781595930101 |
| DOIs | |
| State | Published - 2005 |
| Externally published | Yes |
| Event | GECCO 2005 - Genetic and Evolutionary Computation Conference - Washington, D.C., United States Duration: Jun 25 2005 → Jun 29 2005 |
Publication series
| Name | GECCO 2005 - Genetic and Evolutionary Computation Conference |
|---|---|
| Volume | 2005-January |
Conference
| Conference | GECCO 2005 - Genetic and Evolutionary Computation Conference |
|---|---|
| Country/Territory | United States |
| City | Washington, D.C. |
| Period | 6/25/05 → 6/29/05 |
Bibliographical note
Publisher Copyright:© 2005 ACM.
Keywords
- automatic code generation
- grammatical evolution
- verilog
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