Automatic verilog code generation through grammatical evolution

Ulya R. Karpuzcu

doi:10.1145/1102256.1102346

Automatic verilog code generation through grammatical evolution

Ulya R. Karpuzcu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Scopus citations

Abstract

This work aims to investigate the automatic generation of Verilog code, representing digital circuits through Grammatical Evolution (GE). Preliminary tests using a simple full adder generation problem have been performed.

Original language	English (US)
Title of host publication	GECCO 2005 - Genetic and Evolutionary Computation Conference
Publisher	Association for Computing Machinery
Pages	394-397
Number of pages	4
ISBN (Print)	1595930108, 9781595930101
DOIs	https://doi.org/10.1145/1102256.1102346
State	Published - 2005
Externally published	Yes
Event	GECCO 2005 - Genetic and Evolutionary Computation Conference - Washington, D.C., United States Duration: Jun 25 2005 → Jun 29 2005

Publication series

Name	GECCO 2005 - Genetic and Evolutionary Computation Conference
Volume	2005-January

Conference

Conference	GECCO 2005 - Genetic and Evolutionary Computation Conference
Country/Territory	United States
City	Washington, D.C.
Period	6/25/05 → 6/29/05

Bibliographical note

Publisher Copyright:
© 2005 ACM.

Keywords

automatic code generation
grammatical evolution
verilog

Publisher link

10.1145/1102256.1102346

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Automatic verilog code generation through grammatical evolution. / Karpuzcu, Ulya R.
GECCO 2005 - Genetic and Evolutionary Computation Conference. Association for Computing Machinery, 2005. p. 394-397 (GECCO 2005 - Genetic and Evolutionary Computation Conference; Vol. 2005-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Karpuzcu, UR 2005, Automatic verilog code generation through grammatical evolution. in GECCO 2005 - Genetic and Evolutionary Computation Conference. GECCO 2005 - Genetic and Evolutionary Computation Conference, vol. 2005-January, Association for Computing Machinery, pp. 394-397, GECCO 2005 - Genetic and Evolutionary Computation Conference, Washington, D.C., United States, 6/25/05. https://doi.org/10.1145/1102256.1102346

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abstract = "This work aims to investigate the automatic generation of Verilog code, representing digital circuits through Grammatical Evolution (GE). Preliminary tests using a simple full adder generation problem have been performed.",

keywords = "automatic code generation, grammatical evolution, verilog",

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language = "English (US)",

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AB - This work aims to investigate the automatic generation of Verilog code, representing digital circuits through Grammatical Evolution (GE). Preliminary tests using a simple full adder generation problem have been performed.

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M3 - Conference contribution

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T3 - GECCO 2005 - Genetic and Evolutionary Computation Conference

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BT - GECCO 2005 - Genetic and Evolutionary Computation Conference

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ER -

Automatic verilog code generation through grammatical evolution

Abstract

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Conference

Bibliographical note

Keywords

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