Automatic verilog code generation through grammatical evolution

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

This work aims to investigate the automatic generation of Verilog code, representing digital circuits through Grammatical Evolution (GE). Preliminary tests using a simple full adder generation problem have been performed.

Original languageEnglish (US)
Title of host publicationGECCO 2005 - Genetic and Evolutionary Computation Conference
PublisherAssociation for Computing Machinery
Pages394-397
Number of pages4
ISBN (Print)1595930108, 9781595930101
DOIs
StatePublished - 2005
Externally publishedYes
EventGECCO 2005 - Genetic and Evolutionary Computation Conference - Washington, D.C., United States
Duration: Jun 25 2005Jun 29 2005

Publication series

NameGECCO 2005 - Genetic and Evolutionary Computation Conference
Volume2005-January

Conference

ConferenceGECCO 2005 - Genetic and Evolutionary Computation Conference
Country/TerritoryUnited States
CityWashington, D.C.
Period6/25/056/29/05

Bibliographical note

Publisher Copyright:
© 2005 ACM.

Keywords

  • automatic code generation
  • grammatical evolution
  • verilog

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