Automatic verification of instruction set simulation using synchronized state comparison

B. Glamm, D. J. Lilja

Research output: Contribution to journalConference articlepeer-review

4 Scopus citations


Instruction-level simulation is the basis for much research in computer architecture. Typically, the simulators used for this type of research are verified by comparing the outputs of a simulated benchmark program and the outputs of the same program when run on a real machine - the simulator is "verified" if the outputs are the same. In the case of some benchmark programs, however, it is possible that significant fractions of the benchmark would not be executed due to minor differences or errors in the simulator, which would limit the usefulness of the results of the simulations. This paper presents a novel method for verifying instruction-level simulators via step-by-step register state comparison to a hardware implementation. A description of a sample implementation of this verification method is presented, along with a discussion of specific implementation issues. The verification speed of 1000-5000 instructions per second on a 300 MHz MIPS R12000 is a concern, but possible ways to address this limitation are described.

Original languageEnglish (US)
Pages (from-to)72-77
Number of pages6
JournalProceedings of the IEEE Annual Simulation Symposium
StatePublished - Jan 1 2001
Event34th Annual Simulation Symposium (SS 2001) - Seattle, WA, United States
Duration: Apr 22 2000Apr 26 2000


Dive into the research topics of 'Automatic verification of instruction set simulation using synchronized state comparison'. Together they form a unique fingerprint.

Cite this