Automatic compiler based FPGA accelerator for CNN training

Shreyas Kolala Venkataramanaiah; Yufei Ma; Shihui Yin; Eriko Nurvithadhi; Aravind Dasu; Yu Cao; Jae Sun Seo

doi:10.1109/FPL.2019.00034

Automatic compiler based FPGA accelerator for CNN training

Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvithadhi, Aravind Dasu, Yu Cao, Jae Sun Seo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

39 Scopus citations

Abstract

Training of convolutional neural networks (CNNs) on embedded platforms to support on-device learning is earning vital importance in recent days. Designing flexible training hardware is much more challenging than inference hardware, due to design complexity and large computation/memory requirement. In this work, we present an automatic compiler based FPGA accelerator with 16-bit fixed-point precision for complete CNN training, including Forward Pass (FP), Backward Pass (BP) and Weight Update (WU). We implemented an optimized RTL library to perform training-specific tasks and developed an RTL compiler to automatically generate FPGA-synthesizable RTL based on user-defined constraints. We present a new cyclic weight storage/access scheme for on-chip BRAM and off-chip DRAM to efficiently implement non-transpose and transpose operations during FP and BP phases, respectively. Representative CNNs for CIFAR-10 dataset are implemented and trained on Intel Stratix 10 GX FPGA using proposed hardware architecture, demonstrating up to 479 GOPS performance.

Original language	English (US)
Title of host publication	Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019
Editors	Ioannis Sourdis, Christos-Savvas Bouganis, Carlos Alvarez, Leonel Antonio Toledo Diaz, Pedro Valero, Xavier Martorell
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	166-172
Number of pages	7
ISBN (Electronic)	9781728148847
DOIs	https://doi.org/10.1109/FPL.2019.00034
State	Published - Sep 2019
Externally published	Yes
Event	29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019 - Barcelona, Spain Duration: Sep 9 2019 → Sep 13 2019

Publication series

Name	Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019

Conference

Conference	29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019
Country/Territory	Spain
City	Barcelona
Period	9/9/19 → 9/13/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Keywords

Back-propagation
Convolution neural networks
FPGA
Hardware accelerator
Neural network training

Publisher link

10.1109/FPL.2019.00034

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Venkataramanaiah, S. K., Ma, Y., Yin, S., Nurvithadhi, E., Dasu, A., Cao, Y., & Seo, J. S. (2019). Automatic compiler based FPGA accelerator for CNN training. In I. Sourdis, C.-S. Bouganis, C. Alvarez, L. A. Toledo Diaz, P. Valero, & X. Martorell (Eds.), Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019 (pp. 166-172). Article 8892195 (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2019.00034

Automatic compiler based FPGA accelerator for CNN training. / Venkataramanaiah, Shreyas Kolala; Ma, Yufei; Yin, Shihui et al.
Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. ed. / Ioannis Sourdis; Christos-Savvas Bouganis; Carlos Alvarez; Leonel Antonio Toledo Diaz; Pedro Valero; Xavier Martorell. Institute of Electrical and Electronics Engineers Inc., 2019. p. 166-172 8892195 (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Venkataramanaiah, SK, Ma, Y, Yin, S, Nurvithadhi, E, Dasu, A, Cao, Y & Seo, JS 2019, Automatic compiler based FPGA accelerator for CNN training. in I Sourdis, C-S Bouganis, C Alvarez, LA Toledo Diaz, P Valero & X Martorell (eds), Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019., 8892195, Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019, Institute of Electrical and Electronics Engineers Inc., pp. 166-172, 29th International Conferenceon Field-Programmable Logic and Applications, FPL 2019, Barcelona, Spain, 9/9/19. https://doi.org/10.1109/FPL.2019.00034

Venkataramanaiah SK, Ma Y, Yin S, Nurvithadhi E, Dasu A, Cao Y et al. Automatic compiler based FPGA accelerator for CNN training. In Sourdis I, Bouganis CS, Alvarez C, Toledo Diaz LA, Valero P, Martorell X, editors, Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 166-172. 8892195. (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019). doi: 10.1109/FPL.2019.00034

Venkataramanaiah, Shreyas Kolala ; Ma, Yufei ; Yin, Shihui et al. / Automatic compiler based FPGA accelerator for CNN training. Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019. editor / Ioannis Sourdis ; Christos-Savvas Bouganis ; Carlos Alvarez ; Leonel Antonio Toledo Diaz ; Pedro Valero ; Xavier Martorell. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 166-172 (Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019).

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Automatic compiler based FPGA accelerator for CNN training

Abstract

Publication series

Conference

Bibliographical note

Keywords

Publisher link

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