Automated layout synthesis in the YASC silicon compiler

In this paper, we present algorithms and experimental results for an automated layout synthesis procedure that is used in a high-level silicon compiler. The techniques consist of a unique approach to generalized cell synthesis, together with a novel solution of the placement and routing problem. Our algorithms take advantage of a larger space of possible solutions than is available in conventional, fixed-cell approaches to achieve compact and efficient layouts. First, our techniques for cell synthesis are presented. Then, we describe our placement algorithm, in which the locations of the cells are determined by signal-flow considerations. Next, our pin permutation procedure is described. These permutations are not limited to the relatively few cases of logically equivalent pins, but rather, can exploit a much larger set of transformations involving the re-arrangement of the inner structure of the cells themselves. Finally, our techniques for both global and channel routing are discussed. Experimental results for a complete chip layout are included.