Area-power-time efficient pipeline-interleaved architectures for wave digital filters

Various forms of pipelining are explored for low power implementation of lattice wave digital filters realized with 3-port adaptors. In these filters, the time performance of pipelining is constrained by recursion. Using the fastest, block pipelined architecture as a reference point, it is shown that additional levels of pipelining can be applied to reduce the power consumption, at the expense of slightly changing the maximum sample rate. In one case power is reduced by 65% with only a modest speed penalty. Area increases due to additional pipeline registers can be more than offset if the consequent interleaving capability is utilized.