Area-power-time efficient pipeline-interleaved architectures for wave digital filters

S. Summerfield, Z. F. Wang, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Various forms of pipelining are explored for low power implementation of lattice wave digital filters realized with 3-port adaptors. In these filters, the time performance of pipelining is constrained by recursion. Using the fastest, block pipelined architecture as a reference point, it is shown that additional levels of pipelining can be applied to reduce the power consumption, at the expense of slightly changing the maximum sample rate. In one case power is reduced by 65% with only a modest speed penalty. Area increases due to additional pipeline registers can be more than offset if the consequent interleaving capability is utilized.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
ISBN (Print)0780354710
StatePublished - Jan 1 1999
EventProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA
Duration: May 30 1999Jun 2 1999

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Other

OtherProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
CityOrlando, FL, USA
Period5/30/996/2/99

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