AREA-EFFICIENT HIGH SPEED VLSI ADAPTIVE FILTER ARCHITECTURES.

It is shown that adaptive filters can be implemented in an area-efficient manner by first using pipelining to the maximum possible extent, and then using block processing in combination with pipelining if further increase in sampling rate is needed. With the use of a decomposition technique, high-speed realizations can be achieved using pipelining with a logarithmic increase in hardware. Pipelined word-parallel realizations of high-sampling-rate adaptive lattice filters are derived, using the techniques of look-ahead computation, decomposition, and incremental output computation. Combining these techniques makes it possible to achieve asymptotically optimal complexity realizations of high-speed adaptive lattice filters and provides a system solution to high-speed adaptive filtering. The adaptive lattice filter structures are shown to be ideal for high-sampling-rate implementations.