AREA-EFFICIENT HIGH SPEED VLSI ADAPTIVE FILTER ARCHITECTURES.

Keshab Kumar Parhi, David G. Messerschmitt

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

It is shown that adaptive filters can be implemented in an area-efficient manner by first using pipelining to the maximum possible extent, and then using block processing in combination with pipelining if further increase in sampling rate is needed. With the use of a decomposition technique, high-speed realizations can be achieved using pipelining with a logarithmic increase in hardware. Pipelined word-parallel realizations of high-sampling-rate adaptive lattice filters are derived, using the techniques of look-ahead computation, decomposition, and incremental output computation. Combining these techniques makes it possible to achieve asymptotically optimal complexity realizations of high-speed adaptive lattice filters and provides a system solution to high-speed adaptive filtering. The adaptive lattice filter structures are shown to be ideal for high-sampling-rate implementations.

Original languageEnglish (US)
Pages (from-to)858-862
Number of pages5
JournalConference Record - International Conference on Communications
StatePublished - Dec 1 1987

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Adaptive filters
Sampling
Decomposition
Adaptive filtering
Hardware
Processing

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AREA-EFFICIENT HIGH SPEED VLSI ADAPTIVE FILTER ARCHITECTURES. / Parhi, Keshab Kumar; Messerschmitt, David G.

In: Conference Record - International Conference on Communications, 01.12.1987, p. 858-862.

Research output: Contribution to journalArticle

@article{fefd0d6700f44d8c8754ce245db75a1e,
title = "AREA-EFFICIENT HIGH SPEED VLSI ADAPTIVE FILTER ARCHITECTURES.",
abstract = "It is shown that adaptive filters can be implemented in an area-efficient manner by first using pipelining to the maximum possible extent, and then using block processing in combination with pipelining if further increase in sampling rate is needed. With the use of a decomposition technique, high-speed realizations can be achieved using pipelining with a logarithmic increase in hardware. Pipelined word-parallel realizations of high-sampling-rate adaptive lattice filters are derived, using the techniques of look-ahead computation, decomposition, and incremental output computation. Combining these techniques makes it possible to achieve asymptotically optimal complexity realizations of high-speed adaptive lattice filters and provides a system solution to high-speed adaptive filtering. The adaptive lattice filter structures are shown to be ideal for high-sampling-rate implementations.",
author = "Parhi, {Keshab Kumar} and Messerschmitt, {David G.}",
year = "1987",
month = "12",
day = "1",
language = "English (US)",
pages = "858--862",
journal = "Conference Record - International Conference on Communications",
issn = "0536-1486",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - AREA-EFFICIENT HIGH SPEED VLSI ADAPTIVE FILTER ARCHITECTURES.

AU - Parhi, Keshab Kumar

AU - Messerschmitt, David G.

PY - 1987/12/1

Y1 - 1987/12/1

N2 - It is shown that adaptive filters can be implemented in an area-efficient manner by first using pipelining to the maximum possible extent, and then using block processing in combination with pipelining if further increase in sampling rate is needed. With the use of a decomposition technique, high-speed realizations can be achieved using pipelining with a logarithmic increase in hardware. Pipelined word-parallel realizations of high-sampling-rate adaptive lattice filters are derived, using the techniques of look-ahead computation, decomposition, and incremental output computation. Combining these techniques makes it possible to achieve asymptotically optimal complexity realizations of high-speed adaptive lattice filters and provides a system solution to high-speed adaptive filtering. The adaptive lattice filter structures are shown to be ideal for high-sampling-rate implementations.

AB - It is shown that adaptive filters can be implemented in an area-efficient manner by first using pipelining to the maximum possible extent, and then using block processing in combination with pipelining if further increase in sampling rate is needed. With the use of a decomposition technique, high-speed realizations can be achieved using pipelining with a logarithmic increase in hardware. Pipelined word-parallel realizations of high-sampling-rate adaptive lattice filters are derived, using the techniques of look-ahead computation, decomposition, and incremental output computation. Combining these techniques makes it possible to achieve asymptotically optimal complexity realizations of high-speed adaptive lattice filters and provides a system solution to high-speed adaptive filtering. The adaptive lattice filter structures are shown to be ideal for high-sampling-rate implementations.

UR - http://www.scopus.com/inward/record.url?scp=0023534174&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0023534174&partnerID=8YFLogxK

M3 - Article

SP - 858

EP - 862

JO - Conference Record - International Conference on Communications

JF - Conference Record - International Conference on Communications

SN - 0536-1486

ER -