This paper exploits the similarity between the two stages of belief propagation decoding algorithm for low density parity check codes to derive an area efficient design that re-maps the check node functional units and variable node functional units into the same hardware. Consequently, the novel approach could reduce the logic core size by approximately 21% without any performance degradation. In addition, the proposed approach improves the hardware utilization efficiency as well.
|Original language||English (US)|
|Journal||ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings|
|State||Published - Sep 27 2004|
|Event||Proceedings - IEEE International Conference on Acoustics, Speech, and Signal Processing - Montreal, Que, Canada|
Duration: May 17 2004 → May 21 2004