This paper presents novel structures for lattice IIR digital filters that are well suited for stochastic computing. Stochastic computing systems require fewer logic gates and are inherently fault-tolerant. Thus, these structures are appropriate for nanoscale CMOS technologies. It has been shown that stochastic IIR digital filters can be implemented using the basic lattice structure. However, these implementations require use of binary multipliers and, thus, suffer from increased hardware complexity. The key contribution of this paper lies in demonstrating that the proposed modified lattice IIR structures can be implemented using stochastic logic without requiring any binary multiplier except left-shift operations. A modified lattice structure is derived using scale factor si = 1 ± ki in the Schur Algorithm. Two architectures are proposed for stochastic lattice IIR filters. The first is based on the normalized lattice structure, where states are orthonormal, which prevents state overflow. The second is based on the proposed modified lattice structure. Binary multipliers are replaced by left-shift operations in the proposed structures. The proposed architectures require fewer stochastic number generators and stochastic-to-binary converters. Therefore, the area for the proposed design is 90% less than the two's complement lattice filters. Additionally, compared to previous stochastic computing design, the hardware complexity is reduced by 60%. Experimental results show that the output signal-to- error power ratio of the first implementation for narrow-band IIR filter increases by an order of magnitude, compared to previous stochastic designs. Simulation results also demonstrate high fault tolerance of the proposed structures. Synthesis results show excellent timing scalability of the proposed stochastic IIR filters with respect to the filter order, compared to 2's complement implementations.