Architectures for Recursive Digital Filters Using Stochastic Computing

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

This paper addresses implementation of digital IIR filters using stochastic computing. Stochastic computing requires fewer logic gates and is inherently fault-tolerant. Thus, these structures are well suited for nanoscale CMOS technologies. While it is easy to realize FIR filters using stochastic computing, implementation of IIR digital filters is non-trivial. Stochastic logic assumes independence of input signals; however, feedback in IIR digital filters leads to correlation of input signals, and the independence assumption is violated. This paper demonstrates that, despite feedback in IIR filters, these filters can be implemented using stochastic logic. The key to stochastic implementation is selection of an IIR filter structure where the states are orthogonal and are, therefore, uncorrelated. Two categories of architectures are presented for stochastic IIR digital filters. One category is based on the basic lattice filter representation where the states are orthogonal, and the other is based on the normalized lattice filter representation where states are orthonormal. For each category, three stochastic implementations are introduced. The first is based on a state-space description of the IIR filter derived from the lattice filter structure. The second is based on transforming the lattice IIR digital filter into an equivalent form that can exploit the novel scaling approach developed for inner product computations. The third is optimized stochastic implementation with reduced number of binary multipliers. Simulation results demonstrate high signal-to-error ratio and fault tolerance in these structures. Furthermore, hardware synthesis results show that these filter structures require lower hardware area and power compared to two's complement realizations.

Original languageEnglish (US)
Article number7450670
Pages (from-to)3705-3718
Number of pages14
JournalIEEE Transactions on Signal Processing
Volume64
Issue number14
DOIs
StatePublished - Jul 15 2016

Fingerprint

IIR filters
Digital filters
Feedback
Hardware
Logic gates
FIR filters
Fault tolerance

Keywords

  • fault tolerance
  • IIR filter
  • lattice structure
  • normalization
  • scaling
  • state-space description
  • Stochastic computing
  • stochastic digital filter

Cite this

Architectures for Recursive Digital Filters Using Stochastic Computing. / Liu, Yin; Parhi, Keshab K.

In: IEEE Transactions on Signal Processing, Vol. 64, No. 14, 7450670, 15.07.2016, p. 3705-3718.

Research output: Contribution to journalArticle

@article{860adea0801442ba9fbc37a7a76b3bd2,
title = "Architectures for Recursive Digital Filters Using Stochastic Computing",
abstract = "This paper addresses implementation of digital IIR filters using stochastic computing. Stochastic computing requires fewer logic gates and is inherently fault-tolerant. Thus, these structures are well suited for nanoscale CMOS technologies. While it is easy to realize FIR filters using stochastic computing, implementation of IIR digital filters is non-trivial. Stochastic logic assumes independence of input signals; however, feedback in IIR digital filters leads to correlation of input signals, and the independence assumption is violated. This paper demonstrates that, despite feedback in IIR filters, these filters can be implemented using stochastic logic. The key to stochastic implementation is selection of an IIR filter structure where the states are orthogonal and are, therefore, uncorrelated. Two categories of architectures are presented for stochastic IIR digital filters. One category is based on the basic lattice filter representation where the states are orthogonal, and the other is based on the normalized lattice filter representation where states are orthonormal. For each category, three stochastic implementations are introduced. The first is based on a state-space description of the IIR filter derived from the lattice filter structure. The second is based on transforming the lattice IIR digital filter into an equivalent form that can exploit the novel scaling approach developed for inner product computations. The third is optimized stochastic implementation with reduced number of binary multipliers. Simulation results demonstrate high signal-to-error ratio and fault tolerance in these structures. Furthermore, hardware synthesis results show that these filter structures require lower hardware area and power compared to two's complement realizations.",
keywords = "fault tolerance, IIR filter, lattice structure, normalization, scaling, state-space description, Stochastic computing, stochastic digital filter",
author = "Yin Liu and Parhi, {Keshab K}",
year = "2016",
month = "7",
day = "15",
doi = "10.1109/TSP.2016.2552513",
language = "English (US)",
volume = "64",
pages = "3705--3718",
journal = "IEEE Transactions on Signal Processing",
issn = "1053-587X",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "14",

}

TY - JOUR

T1 - Architectures for Recursive Digital Filters Using Stochastic Computing

AU - Liu, Yin

AU - Parhi, Keshab K

PY - 2016/7/15

Y1 - 2016/7/15

N2 - This paper addresses implementation of digital IIR filters using stochastic computing. Stochastic computing requires fewer logic gates and is inherently fault-tolerant. Thus, these structures are well suited for nanoscale CMOS technologies. While it is easy to realize FIR filters using stochastic computing, implementation of IIR digital filters is non-trivial. Stochastic logic assumes independence of input signals; however, feedback in IIR digital filters leads to correlation of input signals, and the independence assumption is violated. This paper demonstrates that, despite feedback in IIR filters, these filters can be implemented using stochastic logic. The key to stochastic implementation is selection of an IIR filter structure where the states are orthogonal and are, therefore, uncorrelated. Two categories of architectures are presented for stochastic IIR digital filters. One category is based on the basic lattice filter representation where the states are orthogonal, and the other is based on the normalized lattice filter representation where states are orthonormal. For each category, three stochastic implementations are introduced. The first is based on a state-space description of the IIR filter derived from the lattice filter structure. The second is based on transforming the lattice IIR digital filter into an equivalent form that can exploit the novel scaling approach developed for inner product computations. The third is optimized stochastic implementation with reduced number of binary multipliers. Simulation results demonstrate high signal-to-error ratio and fault tolerance in these structures. Furthermore, hardware synthesis results show that these filter structures require lower hardware area and power compared to two's complement realizations.

AB - This paper addresses implementation of digital IIR filters using stochastic computing. Stochastic computing requires fewer logic gates and is inherently fault-tolerant. Thus, these structures are well suited for nanoscale CMOS technologies. While it is easy to realize FIR filters using stochastic computing, implementation of IIR digital filters is non-trivial. Stochastic logic assumes independence of input signals; however, feedback in IIR digital filters leads to correlation of input signals, and the independence assumption is violated. This paper demonstrates that, despite feedback in IIR filters, these filters can be implemented using stochastic logic. The key to stochastic implementation is selection of an IIR filter structure where the states are orthogonal and are, therefore, uncorrelated. Two categories of architectures are presented for stochastic IIR digital filters. One category is based on the basic lattice filter representation where the states are orthogonal, and the other is based on the normalized lattice filter representation where states are orthonormal. For each category, three stochastic implementations are introduced. The first is based on a state-space description of the IIR filter derived from the lattice filter structure. The second is based on transforming the lattice IIR digital filter into an equivalent form that can exploit the novel scaling approach developed for inner product computations. The third is optimized stochastic implementation with reduced number of binary multipliers. Simulation results demonstrate high signal-to-error ratio and fault tolerance in these structures. Furthermore, hardware synthesis results show that these filter structures require lower hardware area and power compared to two's complement realizations.

KW - fault tolerance

KW - IIR filter

KW - lattice structure

KW - normalization

KW - scaling

KW - state-space description

KW - Stochastic computing

KW - stochastic digital filter

UR - http://www.scopus.com/inward/record.url?scp=84976351221&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84976351221&partnerID=8YFLogxK

U2 - 10.1109/TSP.2016.2552513

DO - 10.1109/TSP.2016.2552513

M3 - Article

AN - SCOPUS:84976351221

VL - 64

SP - 3705

EP - 3718

JO - IEEE Transactions on Signal Processing

JF - IEEE Transactions on Signal Processing

SN - 1053-587X

IS - 14

M1 - 7450670

ER -