Architectures for multi-gigabit wire-linked clock and data recovery

Ming Ta Hsieh, Gerald E. Sobelman

Research output: Contribution to journalArticle

56 Scopus citations

Abstract

Clock and data recovery (CDR) architectures used in high-speed wire-linked communication receivers are often shown as PLL or DLL based topologies. However, there are many other types of CDR architectures such as phase-interpolator, oversampling and injection locked based topologies. The best choice for the CDR topology will depend on the application and the specification requirements. This paper presents an overview and comparative study of the most commonly used CDR architectures. This analysis includes the circuit structures, design challenges, major performance limitations and primary applications. Finally, the tradeoffs among the various CDR architectures are summarized.

Original languageEnglish (US)
Pages (from-to)45-57
Number of pages13
JournalIEEE Circuits and Systems Magazine
Volume8
Issue number4
DOIs
StatePublished - Dec 1 2008

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