Architectures for lattice structure based orthonormal discrete wavelet transforms

Tracy C. Denk, Keshab K Parhi

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

This paper presents efficient single-rate architectures for the orthonormal discrete wavelet transform (DWT). Folded and digit-serial architectures are derived from an efficient lattice implementation of two-channel FIR paraunitary systems known as the quadrature mirror filter (QMF) lattice. Folded architectures are derived by applying systematic folding techniques to multirate systems. For digit-serial architectures, we show that any two-channel subband system can be implemented using digit-serial processing techniques by utilizing the polyphase decomposition. Using this result, we describe an orthonormal DWT architecture which uses the QMF lattice structure and digit-serial processing techniques. The number of multipliers and adders required for both the folded and digit-serial lattice-based architectures approaches one-half the number required to implement similar systems based on direct-form filter implementations as the order of the FIR filters becomes large. This makes folded and digit-serial QMF lattice structures attractive choices for applications of the orthonormal DWT which require low area and low power dissipation.

Original languageEnglish (US)
Pages (from-to)259-270
Number of pages12
JournalProceedings of the International Conference on Application Specific Array Processors
StatePublished - Dec 1 1994

Fingerprint

Discrete wavelet transforms
Digital filters
Adders
FIR filters
Processing
Energy dissipation
Decomposition

Cite this

@article{364813a7c8b441478ef3d15c8cd46c90,
title = "Architectures for lattice structure based orthonormal discrete wavelet transforms",
abstract = "This paper presents efficient single-rate architectures for the orthonormal discrete wavelet transform (DWT). Folded and digit-serial architectures are derived from an efficient lattice implementation of two-channel FIR paraunitary systems known as the quadrature mirror filter (QMF) lattice. Folded architectures are derived by applying systematic folding techniques to multirate systems. For digit-serial architectures, we show that any two-channel subband system can be implemented using digit-serial processing techniques by utilizing the polyphase decomposition. Using this result, we describe an orthonormal DWT architecture which uses the QMF lattice structure and digit-serial processing techniques. The number of multipliers and adders required for both the folded and digit-serial lattice-based architectures approaches one-half the number required to implement similar systems based on direct-form filter implementations as the order of the FIR filters becomes large. This makes folded and digit-serial QMF lattice structures attractive choices for applications of the orthonormal DWT which require low area and low power dissipation.",
author = "Denk, {Tracy C.} and Parhi, {Keshab K}",
year = "1994",
month = "12",
day = "1",
language = "English (US)",
pages = "259--270",
journal = "International Conference on Application-Specific Systems, Architectures and Processors, Proceedings",
issn = "1063-6862",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Architectures for lattice structure based orthonormal discrete wavelet transforms

AU - Denk, Tracy C.

AU - Parhi, Keshab K

PY - 1994/12/1

Y1 - 1994/12/1

N2 - This paper presents efficient single-rate architectures for the orthonormal discrete wavelet transform (DWT). Folded and digit-serial architectures are derived from an efficient lattice implementation of two-channel FIR paraunitary systems known as the quadrature mirror filter (QMF) lattice. Folded architectures are derived by applying systematic folding techniques to multirate systems. For digit-serial architectures, we show that any two-channel subband system can be implemented using digit-serial processing techniques by utilizing the polyphase decomposition. Using this result, we describe an orthonormal DWT architecture which uses the QMF lattice structure and digit-serial processing techniques. The number of multipliers and adders required for both the folded and digit-serial lattice-based architectures approaches one-half the number required to implement similar systems based on direct-form filter implementations as the order of the FIR filters becomes large. This makes folded and digit-serial QMF lattice structures attractive choices for applications of the orthonormal DWT which require low area and low power dissipation.

AB - This paper presents efficient single-rate architectures for the orthonormal discrete wavelet transform (DWT). Folded and digit-serial architectures are derived from an efficient lattice implementation of two-channel FIR paraunitary systems known as the quadrature mirror filter (QMF) lattice. Folded architectures are derived by applying systematic folding techniques to multirate systems. For digit-serial architectures, we show that any two-channel subband system can be implemented using digit-serial processing techniques by utilizing the polyphase decomposition. Using this result, we describe an orthonormal DWT architecture which uses the QMF lattice structure and digit-serial processing techniques. The number of multipliers and adders required for both the folded and digit-serial lattice-based architectures approaches one-half the number required to implement similar systems based on direct-form filter implementations as the order of the FIR filters becomes large. This makes folded and digit-serial QMF lattice structures attractive choices for applications of the orthonormal DWT which require low area and low power dissipation.

UR - http://www.scopus.com/inward/record.url?scp=0028571421&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028571421&partnerID=8YFLogxK

M3 - Article

SP - 259

EP - 270

JO - International Conference on Application-Specific Systems, Architectures and Processors, Proceedings

JF - International Conference on Application-Specific Systems, Architectures and Processors, Proceedings

SN - 1063-6862

ER -