ARCHITECTURE CONSIDERATIONS FOR HIGH SPEED RECURSIVE FILTERING.

Keshab Kumar Parhi, Wen Lung Chen, David G. Messerschmitt

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

Pipeline interleaving in the incremental block-state structure for pipelined block implementation of high sampling rate recursive digital filters is introduced. An approach to the state update implementation using a novel decomposition technique is presented. This novel state update implementation, and the incremental output computation (based on the incremental block-state structure) lead to an efficient implementation of pipelined block recursive digital filters of (asymptotic) complexity linear in filter order (based on a quasi-diagonal state update matrix) and block size. The complexity of this implementation as measured by the number of multiplications is asymptotically same as that of nonrecursive systems independent of the implementation methodology. However, for smaller block sizes, bit-level pipelined bit-serial word-parallel implementation may lead to reduced complexity realization as compared to bit-level pipelined bit-parallel word-parallel implementation. This comparison is assisted by the concept of an implementable delay operator introduced by the authors.

Original languageEnglish (US)
Pages (from-to)374-377
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Jan 1 1987

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Digital filters
Pipelines
Sampling
Decomposition

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ARCHITECTURE CONSIDERATIONS FOR HIGH SPEED RECURSIVE FILTERING. / Parhi, Keshab Kumar; Chen, Wen Lung; Messerschmitt, David G.

In: Proceedings - IEEE International Symposium on Circuits and Systems, 01.01.1987, p. 374-377.

Research output: Contribution to journalArticle

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