Abstract
Polynomial multiplication over the quotient ring is a critical operation in Ring Learning with Errors (Ring-LWE) based cryptosystems that are used for post-quantum cryptography and homomorphic encryption. This operation can be efficiently implemented using number-theoretic transform (NTT)-based architectures. Among these, pipelined parallel NTT-based polynomial multipliers are attractive for cloud computing as these are well suited for high throughput and low latency applications. For a given polynomial length, a pipelined parallel NTT-based multiplier can be designed with varying degrees of parallelism, resulting in different tradeoffs. Higher parallelism reduces latency but increases area and power consumption, and vice versa. In this paper, we develop a predictive model based on synthesized results for pipelined parallel NTT-based polynomial multipliers and analyze design tradeoffs in terms of area, power, energy, area-time product, and area-energy product across parallelism levels up to 128. We predict that, for very long polynomials, area and power differences between designs with varying levels of parallelism become negligible. In contrast, area-time product and energy per polynomial multiplication decrease with increased parallelism. Our findings suggest that, given area and power constraints, the highest feasible level of parallelism optimizes latency, area-time product, and energy per polynomial multiplication.
| Original language | English (US) |
|---|---|
| Title of host publication | Conference Record of the 58th Asilomar Conference on Signals, Systems and Computers, ACSSC 2024 |
| Editors | Michael B. Matthews |
| Publisher | IEEE Computer Society |
| Pages | 1797-1801 |
| Number of pages | 5 |
| ISBN (Electronic) | 9798350354058 |
| DOIs | |
| State | Published - 2024 |
| Event | 58th Asilomar Conference on Signals, Systems and Computers, ACSSC 2024 - Hybrid, Pacific Grove, United States Duration: Oct 27 2024 → Oct 30 2024 |
Publication series
| Name | Conference Record - Asilomar Conference on Signals, Systems and Computers |
|---|---|
| ISSN (Print) | 1058-6393 |
Conference
| Conference | 58th Asilomar Conference on Signals, Systems and Computers, ACSSC 2024 |
|---|---|
| Country/Territory | United States |
| City | Hybrid, Pacific Grove |
| Period | 10/27/24 → 10/30/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- folding
- number theoretic transform (NTT)
- parallel processing
- pipelining
- polynomial multiplication
- Post-quantum cryptography (PQC)
- predictive model
Fingerprint
Dive into the research topics of 'Architectural Tradeoffs for Long Polynomial Modular Multiplication'. Together they form a unique fingerprint.Cite this
- APA
- Standard
- Harvard
- Vancouver
- Author
- BIBTEX
- RIS