Architecting processors to allow voltage/reliability tradeoffs

John Sartori, Rakesh Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

Escalating variations in modern CMOS designs have become a threat to Moore's law. While previous works have proposed techniques for tolerating variations by trading reliability for reduced voltage (energy) [10], the benefits of such techniques are limited, because voltage/reliability tradeoffs in conventional processors often introduce more errors than can be gainfully tolerated [14]. Recent work has proposed circuit and design-level optimizations [14, 15] that manipulate the error rate behavior of a design to increase the potential for energy savings from voltage/reliability tradeoffs. In this paper, we investigate whether architectural optimizations can also manipulate error rate behavior to significantly increase the energy savings from voltage/reliability tradeoffs. To this end, we demonstrate how error rate behavior indeed depends on processor architecture, and that architectural optimizations can be used to manipulate the error rate behavior of a processor. We show that architectural optimizations can significantly enhance voltage/reliability tradeoffs, achieving up to 29% additional energy savings for processors that employ Razor-based error resilience.

Original languageEnglish (US)
Title of host publicationEmbedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11
Pages115-124
Number of pages10
DOIs
StatePublished - Nov 21 2011
EventEmbedded Systems Week 2011, ESWEEK 2011 - 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11 - Taipei, Taiwan, Province of China
Duration: Oct 9 2011Oct 14 2011

Publication series

NameEmbedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11

Other

OtherEmbedded Systems Week 2011, ESWEEK 2011 - 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11
CountryTaiwan, Province of China
CityTaipei
Period10/9/1110/14/11

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Keywords

  • Energy efficiency
  • Error resilience
  • Microarchitecture
  • Timing speculation

Cite this

Sartori, J., & Kumar, R. (2011). Architecting processors to allow voltage/reliability tradeoffs. In Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11 (pp. 115-124). (Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11). https://doi.org/10.1145/2038698.2038718