Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs

S. Rasoul Faraji, Pierre Abillama, Kia Bazargan

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-Time processing is needed, as in 4K video processing, or where hardware resources are limited, as in mobile and IoT devices. We propose a novel, low-cost, low energy, and high-speed approximate constant coefficient multiplier (CCM) using a hybrid binary-unary encoding method. The proposed method implements a CCM using simple routing networks with no logic gates in the unary domain, which results in more efficient multipliers compared to Xilinx LogiCORE IP CCMs and table-based KCM CCMs (Flopoco) on average. We evaluate the proposed multipliers on 2-D discrete cosine transform algorithm as a common DSP module. Post-routing FPGA results show that the proposed multipliers can improve the {area, area × delay, power consumption, and energy-delay product} of a 2-D discrete cosine transform on average by {30%, 33%, 30%, 31%}. Moreover, the throughput of the proposed 2-D discrete cosine transform is on average 5% more than that of the binary architecture implemented using table-based KCM CCMs. We will show that our method has fewer routability issues compared to binary implementations when implementing a DCT core.

Original languageEnglish (US)
Article number29
JournalACM Transactions on Reconfigurable Technology and Systems
Issue number3
StatePublished - Sep 2022

Bibliographical note

Funding Information:
This work was partially funded through a grant from NSF under grant number PFI-TT 2016390. Any opinions, findings and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the US National Science Foundation. Authors’ addresses: S. Rasoul Faraji and K. Bazargan, University of Minnesota, Department of Electrical and Computer Engineering, 4-178 Keller Hall, 200 Union St SE, Minneapolis, MN, 55455; emails: {faraj008, kia}; P. Abillama, University of Michigan, Electrical and Computer Engineering, EECS Building, 1301 Beal Avenue, Ann Arbor, MI, 48109-2122; email: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from © 2021 Association for Computing Machinery. 1936-7406/2021/12-ART29 $15.00

Publisher Copyright:
© 2021 Association for Computing Machinery.


  • Constant coefficient multiplication
  • FIR
  • JPEG
  • stochastic computing
  • unary computing


Dive into the research topics of 'Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs'. Together they form a unique fingerprint.

Cite this