|Original language||English (US)|
|Number of pages||10|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Jul 2005|
Bibliographical noteFunding Information:
Krishnendu Chakrabarty (S’92–M’96–SM’00) received the B.Tech. degree in computer sci-ence and engineering from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees in computer science and engineering from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively, all in computer science and engineering. He is currently Associate Professor of electrical and computer engineering at Duke University, Durham, NC. He is a coauthor of two books: Microelectrofluidic Systems: Modeling and Simula-tion (Boca Raton, FL: CRC, 2002) and Test Resource Partitioning for System-on-a-Chip (Norwell, MA: Kluwer, 2002), and the Editor of SOC (System-on-a-Chip) Testing for Plug and Play Test Automation (Norwell, MA: Kluwer, 2002). He is also a coauthor of the forthcoming book Scal-able Infrastructure for Distributed Sensor Networks (London, U.K.: Springer). He has published over 190 papers in journals and refereed conference proceedings, and he holds a U.S. patent in built-in self-test. His current research projects include the design and testing of system-on-chip integrated circuits; embedded real-time systems; distributed sensor networks; design automation of microfluidics-based biochips; and microfluidics-based chip cooling. Dr. Chakrabarty is a member of ACM and ACM SIGDA, and a member of Sigma Xi. He is an Associate Editor of the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS and the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, and he served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. He is an Associate Editor of ACM Journal on Emerging Technologies in Computing Systems and Editor of the Journal of Electronic Testing: Theory and Applications (JETTA). He serves as a subject area editor for the International Journal of Distributed Sensor Networks. He is a Distinguished Visitor of the IEEE Computer Society for 2005–2007. He serves as Vice Chair of Technical Activities in IEEE’s Test Technology Technical Council, and is a member of the program committees of several IEEE/ACM conferences and workshops. He served as the Tutorial Co-Chair for the 2005 IEEE International Conference on VLSI Design and is the designated Program Co-Chair for the 2005 IEEE Asian Test Symposium. He is a recipient of the National Science Foundation Early Faculty (CAREER) award and the Office of Naval Research Young Investigator award. He is a recipient of a best paper award at the 2001 Design, Automation and Test in Europe (DATE) Conference. He is also a recipient of the Humboldt Research Fellowship from the Alexander von Humboldt Foundation, Germany.
Prof. Ismail is on the Editorial Board of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, on the Editorial Board of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, and a Guest Editor for a special issue of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS on “On-Chip Inductance in High Speed Integrated Circuits.” He was selected as the 2002 IEEE Circuits and Systems Society Outstanding Young Author Award Winner. He also won the National Science Foundation Career Award in 2002. He was given the Best Teacher Award from the Electrical and Computer Engineering Department, Northwestern University, Evanston, IL, in 2003.
Niraj K. Jha (S’85–M’85–SM’93–F’98) received the B.Tech. degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India, in 1981, the M.S. degree in electrical engineering from the State University of New York, Stony Brook, in 1982, and the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign, in 1985. He is currently a Professor of electrical engineering with Princeton University, Princeton, NJ. His research interests include low-power hardware and software design, computer-aided design of integrated circuits and systems, digital system testing, and distributed computing. He is the Director of the Center for Embedded System-on-a-Chip Design, which is funded by New Jersey Commission on Science and Technology. He has coauthored Testing and Reliable Design of CMOS Circuits (Norwell, MA: Kluwer, 1990), High-Level Power Analysis and Optimization (Norwell, MA: Kluwer, 1998), and Testing of Digital Systems (Cambridge, U.K.: Cambridge Univ. Press, 2003). He has also authored three book chapters and authored or coauthored over 250 technical papers. He holds 11 U.S. patents. He is currently the Editor of the Journal of Electronic Testing: Theory and Applications (JETTA), and the Journal of Embedded Computing and has served as a Guest Editor for the JETTA “Special Issue on High-Level Test Synthesis.” Prof. Jha is a Fellow of the Association for Computing Machinery. He has served as an associate editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS —II: ANALOG AND DIGITAL SIGNAL PROCESSING. He is currently editor of the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, and the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. He has also served as the program chairman of the 1992 Workshop on Fault-Tolerant Parallel and Distributed Systems and the 2004 International Conference on Embedded and Ubiquitous Computing. He was the recipient of the AT&T Foundation Award and NEC Preceptorship Award for research excellence, the NCR Award for teaching excellence, and the Princeton University Graduate Mentoring Award. He has coauthored six papers, which have earned the Best Paper Award at ICCD’93, FTCS’97, ICVLSID’98, DAC’99, PDCS’02, and ICVLSID’03. Another paper of his was selected for “The Best of ICCAD: A collection of the best IEEE International Conference on Computer-Aided Design papers of the past 20 years.” Lizy Kurian John (M’00) received the B.S. degree in electronics and telecommunication from University of Kerala, India, and the M.S. degree in computer engineering from University of Texas, El Paso, and the Ph.D. degree in computer engineering from The Pennsylvania State Uni-versity, State College, in 1993.
She is currently an Associate Professor in the Electrical and Computer Engineering Depart-ment at Univerity of Texas (UT), Austin, and is a UT Austin Engineering Foundation Centennial Teaching Fellow. Prior to joining UT Austin in 1996, she was on the faculty at University of South Florida, Tampa. Her research interests include high performance processor and memory archi-tectures, low power design, reconfigurable architectures, rapid prototyping, field programmable gate arrays, and workload characterization. She has published papers in the IEEE TRANSACTIONS ON COMPUTERS, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, ACM/IEEE International Symposium on Computer Architecture (ISCA), IEEE Micro Sympo-sium (MICRO), IEEE High Performance Computer Architecture Symposium (HPCA), ACM International Symposium on Low Power Electronics and Design (ISLPED), and has a patent for a field programmable memory cell array chip. Her research has been supported by the National Science Foundation, the State of Texas Advanced Technology program, DARPA, IBM, Intel, Motorola, DELL, AMD and Microsoft Corporations.
Dr. John has received the NSF CAREER award, Junior Faculty Enhancement Award from Oak Ridge Associated Universities, IBM Austin Center for Advanced Studies (CAS) Fellowship, UT Austin Engineering Foundation Faculty Award (2001), Hal-liburton, Brown and Root Engineering Foundation Young Faculty Award (1999), etc. She is a Member of the IEEE Computer Society and ACM and ACM SIGARCH. She is also a Member of Eta Kappa Nu, Tau Beta Pi, and Phi Kappa Phi.
Ming-Dou Ker (S’92–M’94–SM’97) received the B.S. degree in electronics engineering and the M.S. and Ph.D. degrees from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1986, 1988, and 1993, respectively. In 1994, he joined the Very Large Scale Integration (VLSI) Design Department, Computer and Communication Research Laboratories (CCL), Industrial Technology Research Institute (ITRI), Taiwan, R.O.C., as a Circuit Design Engineer. In 1998, he became a Department Manager with the VLSI Design Division, CCL/ITRI. In 2000, he became an Associate Professor with the De-partment of Electronics Engineering, National Chiao-Tung University. He has been invited to teach or help ESD protection design and latchup prevention by hundreds of design houses and semiconductor companies in Hsinchu, Taiwan, R.O.C., and in Silicon Valley, San Jose, CA. His research interests include reliability and quality design for nanoelectronics and gigascale systems, high-speed or mixed-voltage I/O interface circuits, especial sensor circuits, and semiconductors. In the field of reliability and quality design for CMOS ICs, he has authored or coauthored over 200 technical papers in international journals and conferences. He holds over 180 patents on reliability and quality design for ICs, which including 81 U.S. patents. His inventions on ESD protection design and latchup prevention method have been widely used in modern IC products. Dr. Ker has served as member of the Technical Program Committee and Session Chair of numerous international conferences (including IEEE ISCAS, IEEE AP-ASIC, IEEE SOC, IEEE IRPS, IEEE ISQED, IPFA, EOS/ESD Symposium, VLSI-TSA, IECMAC,). He has served as the Chair ofRF ESD committee of 2004 International EOS/ESD Symposium, and the Vice-Chair of Latchup committee for 2005 IEEE International Reliability and Physics Symposium (IRPS). He also served as the Technical Program Committee Chair of 2002 Taiwan ESD Conference, the General Chair of 2003 Taiwan ESD Conference, the Publication Chair of 2004 IPFA, Steering Committee of 2004 IPFA, and the ESD Program Chair of 2004 International Conference on Electromagnetic Applications and Compatibility. He was the Organizer of the Special Session on ESD Protection Design for Nanoelectronics and Gigascale Systems in ISCAS 2005. Recently, he was invited as the supervisor to the Standard I/O Committee in the Fabless Semiconductor Association (FSA). He also served as active reviewers for many IEEE Transactions and Journals (ED, EDL, DMR, CPT, JSSC, CAS, VLSI). In 2001, he set up the Taiwan ESD Association. He was elected as the first President of Taiwan ESD Association in 2001. Dr. Ker has received many research awards from ITRI, National Science Council, National Chiao-Tung University, and the Dragon Thesis Award from Acer Foundation. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan by Junior Chamber International (JCI).
Dr. Marculescu is the recipient of a National Science Foundation Faculty Career Award (2000–2004), of an ACM-SIGDA Technical Leadership Award (2003), of the Carnegie Institute of Technology George Tallman Ladd Research Award (2004) and a Best Paper Award from IEEE Asia South-Pacific Design Automation COnference (ASPDAC 2005). She is an IEEE Circuits and Systems Society Distinguished Lecturer (2004–2005) and a Member of Executive Board of the ACM Special Interest Group on Design Automation (SIGDA).
Since 1998, he has been with the Computer Science and Engineering Department, Pennsylvania State University, University Park, where he is currently an Associate Professor. His research in-terests are in the areas of energy-aware reliable systems embedded Java, nano/VLSI systems and computer architecture. He has authored and coauthored more than 100 papers in these areas. His current research projects are supported by National Science Foundation, DARPA/MARCO Gi-gascale Silicon Research Center, Office of Naval Research, Semiconductor Research Consortium and Pittsburgh Digital Greenhouse.
Steven M. Nowick received the B.A. degree from Yale University, New Haven, CT, and the Ph.D. degree in computer science from Stanford University, Stanford, CA, in 1993. He is currently an Associate Professor of Computer Science at Columbia University, New York, NY. His Ph.D. dissertation introduced an automated synthesis method for locally clocked asyn-chronous state machines. He was a Guest Co-editor of a special issue of PROCEEDINGS OF THE IEEE on asynchronous design for in February 1999. His general research interests include asyn-chronous circuits, computer-aided digital design, low-power and high-performance digital sys-tems, and logic synthesis. His recent focus has been mainly on asynchronous digital design (CAD tools, high-speed pipelines, applications) and mixed-timing systems. Dr. Nowick was a Co-Founder of the IEEE Async Symposia series, and has twice served as its Program Co-Chair in 1994 and 1999. He was also Program Chair of the 2002 IEEE/ACM International Workshop on Logic and Synthesis (IWLS). He has been a Member of several pro-gram committees, including the Design Automation Conference, the International Conference on Computer-Aided Design, the Design, Automation, and Test in Europe, the Async Symposium, the International Conference on Computer Design, TAU, the IWLS, and VLSI Design Conference. He is currently an Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (since 2001). He received an National Science Foundation (NSF) Faculty Early Career (CAREER) Award in 1995, an Alfred P. Sloan Research Fellowship in 1995, and an NSF Research Initiation Award in 1993. He received Best Paper Awards at the 1991 IEEE International Conference on Computer Design and at the 2000 IEEE Async Symposium. He also received two medium-scale NSF Information Technology Research Awards in 2000.