Application-specific 3D network-on-chip design using simulated allocation

Keyphrases

• Architectural Design 100%
• Three-dimensional Network-on-chip 100%
• Network on chip 100%
• Network-on-chip Architectures 100%
• Network-on-chip Design 100%
• Three-dimensional (3D) 50%
• Technology Integration 50%
• Traffic Flow 50%
• System-on-chip 50%
• Delay Model 50%
• Floorplanning 50%
• On-chip Synthesis 50%
• 3D Network 50%
• Chip Component 50%
• Silicon Integration 50%
• Network Latency 50%
• Design Objectives 50%
• Stochastic Methods 50%
• Chip Temperature 50%
• On-chip Power 50%
• Flow Routing 50%
• Power Model 50%
• Design Problems 50%
• Three-dimensional Environment 50%
• Improved Topologies 50%

Computer Science

• Networks on Chips 100%
• Architecture Design 33%
• Chip Architecture 33%
• Model for Network 16%
• Design Problem 16%
• Chip Temperature 16%
• Synthesis Algorithm 16%
• Network Latency 16%
• Three-Dimensional Environment 16%
• Design Objective 16%
• System-on-Chip 16%