TY - GEN
T1 - Application-specific 3D network-on-chip design using simulated allocation
AU - Zhou, Pingqiang
AU - Yuh, Ping Hung
AU - Sapatnekar, Sachin S.
PY - 2010
Y1 - 2010
N2 - Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).
AB - Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplan-aware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).
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U2 - 10.1109/ASPDAC.2010.5419830
DO - 10.1109/ASPDAC.2010.5419830
M3 - Conference contribution
AN - SCOPUS:77951241020
SN - 9781424457656
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 517
EP - 522
BT - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
T2 - 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Y2 - 18 January 2010 through 21 January 2010
ER -