Abstract
A layout methodology that uses a hierarchical approach, starting with global chip planning followed by bottom-up implementation, is described. The concept of stretchable macrocells is the key to effective employment of this methodology. The author discusses an application of this methodology to VLSI.
| Original language | English (US) |
|---|---|
| Title of host publication | Unknown Host Publication Title |
| Publisher | IEEE |
| Pages | 125-127 |
| Number of pages | 3 |
| State | Published - Dec 1 1984 |