APPLICATION OF A HIERARCHICAL LAYOUT SYSTEM TO VLSI.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A layout methodology that uses a hierarchical approach, starting with global chip planning followed by bottom-up implementation, is described. The concept of stretchable macrocells is the key to effective employment of this methodology. The author discusses an application of this methodology to VLSI.

Original languageEnglish (US)
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages125-127
Number of pages3
StatePublished - Dec 1 1984

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    Rose, F. (1984). APPLICATION OF A HIERARCHICAL LAYOUT SYSTEM TO VLSI. In Unknown Host Publication Title (pp. 125-127). IEEE.