Analytical performance models for RLC interconnects and application to clock optimization

Xuejue Huang; Yu Cao; Dennis Sylvester; Tsu Jae King; Chenming Hu

doi:10.1109/ASIC.2002.1158084

Analytical performance models for RLC interconnects and application to clock optimization

Xuejue Huang, Yu Cao, Dennis Sylvester, Tsu Jae King, Chenming Hu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

A novel analytical approach for RLC interconnect performance analysis is developed. Using the gate and line geometries as inputs, we derive closed-form expressions for propagation delay, rise time, and voltage overshoot at both the driver output and the far end of the interconnect. This analytical approach enables fast and accurate RLC interconnect analysis and design optimization. Application to clock interconnect optimization is demonstrated and design guidelines are proposed.

Original language	English (US)
Title of host publication	Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Editors	John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	353-357
Number of pages	5
ISBN (Electronic)	0780374940
DOIs	https://doi.org/10.1109/ASIC.2002.1158084
State	Published - 2002
Externally published	Yes
Event	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States Duration: Sep 25 2002 → Sep 28 2002

Publication series

Name	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Volume	2002-January
ISSN (Print)	1063-0988

Conference

Conference	15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/Territory	United States
City	Rochester
Period	9/25/02 → 9/28/02

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

Publisher link

10.1109/ASIC.2002.1158084

Find It

Find It at U of M Libraries

Cite this

Huang, X., Cao, Y., Sylvester, D., King, T. J., & Hu, C. (2002). Analytical performance models for RLC interconnects and application to clock optimization. In J. Chickanosky, R. K. Krishnamurthy, & P. R. Mukund (Eds.), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 (pp. 353-357). Article 1158084 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158084

Analytical performance models for RLC interconnects and application to clock optimization. / Huang, Xuejue; Cao, Yu; Sylvester, Dennis et al.
Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. ed. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. p. 353-357 1158084 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Huang, X, Cao, Y, Sylvester, D, King, TJ & Hu, C 2002, Analytical performance models for RLC interconnects and application to clock optimization. in J Chickanosky, RK Krishnamurthy & PR Mukund (eds), Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002., 1158084, Proceedings of the Annual IEEE International ASIC Conference and Exhibit, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 353-357, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158084

Huang X, Cao Y, Sylvester D, King TJ, Hu C. Analytical performance models for RLC interconnects and application to clock optimization. In Chickanosky J, Krishnamurthy RK, Mukund PR, editors, Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 353-357. 1158084. (Proceedings of the Annual IEEE International ASIC Conference and Exhibit). doi: 10.1109/ASIC.2002.1158084

Huang, Xuejue ; Cao, Yu ; Sylvester, Dennis et al. / Analytical performance models for RLC interconnects and application to clock optimization. Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. editor / John Chickanosky ; Ram K. Krishnamurthy ; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 353-357 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit).

@inproceedings{18911a0da4494153892696a8e8826fb2,

title = "Analytical performance models for RLC interconnects and application to clock optimization",

abstract = "A novel analytical approach for RLC interconnect performance analysis is developed. Using the gate and line geometries as inputs, we derive closed-form expressions for propagation delay, rise time, and voltage overshoot at both the driver output and the far end of the interconnect. This analytical approach enables fast and accurate RLC interconnect analysis and design optimization. Application to clock interconnect optimization is demonstrated and design guidelines are proposed.",

author = "Xuejue Huang and Yu Cao and Dennis Sylvester and King, {Tsu Jae} and Chenming Hu",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 ; Conference date: 25-09-2002 Through 28-09-2002",

year = "2002",

doi = "10.1109/ASIC.2002.1158084",

language = "English (US)",

series = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "353--357",

editor = "John Chickanosky and Krishnamurthy, {Ram K.} and P.R. Mukund",

booktitle = "Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002",

}

TY - GEN

T1 - Analytical performance models for RLC interconnects and application to clock optimization

AU - Huang, Xuejue

AU - Cao, Yu

AU - Sylvester, Dennis

AU - King, Tsu Jae

AU - Hu, Chenming

PY - 2002

Y1 - 2002

N2 - A novel analytical approach for RLC interconnect performance analysis is developed. Using the gate and line geometries as inputs, we derive closed-form expressions for propagation delay, rise time, and voltage overshoot at both the driver output and the far end of the interconnect. This analytical approach enables fast and accurate RLC interconnect analysis and design optimization. Application to clock interconnect optimization is demonstrated and design guidelines are proposed.

AB - A novel analytical approach for RLC interconnect performance analysis is developed. Using the gate and line geometries as inputs, we derive closed-form expressions for propagation delay, rise time, and voltage overshoot at both the driver output and the far end of the interconnect. This analytical approach enables fast and accurate RLC interconnect analysis and design optimization. Application to clock interconnect optimization is demonstrated and design guidelines are proposed.

UR - http://www.scopus.com/inward/record.url?scp=27544471932&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=27544471932&partnerID=8YFLogxK

U2 - 10.1109/ASIC.2002.1158084

DO - 10.1109/ASIC.2002.1158084

M3 - Conference contribution

AN - SCOPUS:27544471932

T3 - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

SP - 353

EP - 357

BT - Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002

A2 - Chickanosky, John

A2 - Krishnamurthy, Ram K.

A2 - Mukund, P.R.

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002

Y2 - 25 September 2002 through 28 September 2002

ER -

Analytical performance models for RLC interconnects and application to clock optimization

Abstract

Publication series

Conference

Bibliographical note

Publisher link

Find It

Other files and links

Fingerprint

Cite this