Abstract
Rapid thermal annealing (RTA) is an important step in semiconductor manufacturing. RTA-induced variability due to differences in die layout patterns can significantly contribute to transistor parameter variations, resulting in degraded chip performance and yield. The die layout patterns that drive these variations are related to the distribution of the density of transistors (silicon) and shallow trench isolation (silicon dioxide) across the die, which result in emissivity variations that change the die surface temperature during annealing. While prior art has developed pattern-dependent simulators and provided mitigation techniques for digital design, it has failed to consider the impact of the temperature-dependent thermal conductivity of silicon on RTA effects and has not analyzed the effects on memory. This work develops a novel 3D transient pattern-dependent RTA simulation methodology that accounts for the dependence of the thermal conductivity of silicon on temperature. The simulator is used to both analyze the effects of RTA on memory performance and to propose mitigation strategies for a 7nm FinFET SRAM design. It is shown that RTA effects degrade read and write delays by 16% and 20% and read static noise margin (SNM) by 15%, and the applied mitigation strategies can compensate for these degradations at the cost of a 16% increase in area for a 7.5% tolerance in SNM margin.
| Original language | English (US) |
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| Title of host publication | Proceedings of the 24th International Symposium on Quality Electronic Design, ISQED 2023 |
| Publisher | IEEE Computer Society |
| ISBN (Electronic) | 9798350334753 |
| DOIs | |
| State | Published - 2023 |
| Event | 24th International Symposium on Quality Electronic Design, ISQED 2023 - San Francisco, United States Duration: Apr 5 2023 → Apr 7 2023 |
Publication series
| Name | 2023 24th International Symposium on Quality Electronic Design (ISQED) |
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Conference
| Conference | 24th International Symposium on Quality Electronic Design, ISQED 2023 |
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| Country/Territory | United States |
| City | San Francisco |
| Period | 4/5/23 → 4/7/23 |
Bibliographical note
Funding Information:These changes do not contribute to an increase in the area of the SRAM block as they are made to the peripheral circuitry, which is underutilized and any increase in the number of fins is absorbed. Further, the overall area of the SRAM block is dominated by the four SRAM arrays, as shown in Fig. 2(a). VI. CONCLUSION We develop a pattern-dependent transient RTA simulator that considers the temperature-dependent thermal conductivity of silicon. The simulator is used to analyze the RTA effects on a 16KB SRAM and to suggest variation mitigation strategies. Acknowledgments: This work is supported in part by SK Hynix. We would like to thank Prof. Chris Kim and Meghna Madhusudan for helping with testcases and simulations. REFERENCES
Publisher Copyright:
© 2023 IEEE.